1. Field of the Invention
The present invention relates to a method and to an arrangement for receiving a binary digital signal that may also have phase shifts, utilizing a clock whose frequency is identical to or plesiochronic with the bit rate of the digital signal and whose phase difference compared to this digital signal is arbitrary.
2. Description of the Prior Art
The German published application Ser. No. 34 41 501 Al discloses a circuit arrangement for recognizing and synchronizing a digital signal that compensates phase fluctuations of the incoming signal bits. To that end, it contains a series circuit of a controllable delay line and a decision logic circuit. The former is connected to a delay control unit via address lines and the latter is connected to the delay control unit via control lines. The decision logic circuit is supplied with a system clock via a clock line, the frequency of the system clock corresponding to the bit rate of the digital signal that is to be regenerated and synchronized.
In an ideal, binary digital signal, the leading and trailing edges lie in a fixed grid that is prescribed by the period of the clock frequency. Each deviation of edges from this grid is referred to as jitter. With defined limits, this dare not lead to an information error upon reception.
Two fundamental types of jitter can be distinguished. The first relates to deviations of the times of two successive edges from the prescribed grid; the second relates to phase shifts that build up slowly and that lead to a time shift of more than one period.
In accordance with an earlier proposal U.S. Ser. No. 07/417,150, now U.S. Pat. No. 5,003,561, a sequence of clocks that have approximately identical phase spacings is formed from a clock by way of a delay chain. Short pulses are derived from these clocks. A query pulse that can also be delayed is derived upon the arrival of each edge of a digital signal selected as effective, a presence of pulses being queried with this query pulse via AND gates. By way of set-reset SR flip-flops and AND gates, clocks selected with existing pulses are connected through and, OR operated, are employed as read-in clocks. The overall operating time of these method steps may possibly be dimensioned by the delay of the query pulse such that the effective edge of the read-in clock always appears half a clock period following the effective edge of the digital signal. What is referred to as an effective edge is an edge serving for the derivation of pulses.